bank0		equ		00h
bank1		equ		80h
bank2		equ		100h
bank3		equ		180h

; *** BIT ASSIGNMENTS FOR I/O LINES & TRI-STATING

ADBIOPrtATRIS	equ		TRISB
ADBIOPrtBTRIS	equ		TRISA

ADBPin		equ		RA4	 	; Port A Pin used for ADB
ADBAltPin	equ		RB0	 	; Port B Pin used for ADB (currently unused)
ADBIOIDH	equ		RB1		; Unit ID high bit (SW1)
ADBIOIDL	equ		RB2		; Unit ID high bit (SW2)

ADBIOPortB	equ		PORTA
ADBIOPinB1	equ		RA0
ADBIOPinB2	equ		RA1
ADBIOPinB3	equ		RA2
ADBIOPinB4	equ		RA3

ADBIOPortA	equ		PORTB
ADBIOPinA1	equ		RB7
ADBIOPinA2	equ		RB6
ADBIOPinA3	equ		RB5
ADBIOPinA4	equ		RB4

;*** MISC. CONSTANTS

DefaultAddr	equ		07h	 			; default device address to start with (Assigned by Apple)
DefaultID	equ		7Ah				; default ID (Assigned by Apple)
									;   Data storage registers


;*** DATA HANDLER ID MASKS: MASK DATA REGISTER 3b FOR:

SELFTST equ	0FFh	 ; Self-Test mode
LISTEN1 equ	  0h	 ; unconditional address change
LISTEN2 equ	0FEh	 ; address change if no collision detected
DEV_ACT equ	0FDh	 ; address change if device activator is depressed


;*** BITS USED IN THE UPPER NIBBLE OF REGISTER 3a FOR SPECIAL ADB STATUS BITS

Resrvd3 equ	 04h	  ; reserved (Always 0)
Srq_Bit equ	 05h	  ; determines if Host will accept Service Requests
ExpEvnt equ	 06h	  ; indicates an Exceptional Event should take place
Always0 equ	 07h	  ; always set to 0


;*** ADB FLAG BITS IN THE "FLAGS1" REGISTER (F1 indicates 1st Flags register)

F1Attn  equ	 00h	 ; set to know if 2nd Task taking place during Attn
F1Talk  equ  02h     ; indicates to Tlt routine this is a Talk Command
F1Stop  equ	 03h	 ; set to indicate the Data Stop Bit is being sent
F1Lstn  equ	 04h	 ; indicates to Tlt routine this is a Listen Command

F1Rcvd1 equ	 06h	 ; 1st byte of Data Register has been received
F1Cllsn equ	 07h	 ; set to indicate that a collision occurred


;*** FLAG BITS IN THE "FLAGS2" REGISTER (F2 indicates 2nd Flags register)

F2Srq		equ	 	00h				; indicate that Srq should be issued
F2STest		equ		03h				; set to indicate a device Self Test is to be performed
F2SFail		equ		04h				; set to indicate that the Device Self-Test Failed
F2DRcvd		equ		05h				; set when data is received for 2nd Application Task


; Timing Definitions for 8 Mhz clock
; ------------------------------------------------------------------------------

PrSclr1		equ		d'4'			; TMR0 period (microseconds) when prescaler is set to 8
PrSclr2 	equ		d'1'			; TMR0 period (microseconds) when prescaler is set to 2

ATT_MIN 	equ		d'776'/PrSclr1	; Attn lower limit: 800 - 3% tolerance = 776 usecs
ATT_MAX 	equ		d'824'/PrSclr1	; Attn upper limit: 800 + 3% tolerance = 824 usecs
TSK2MIN 	equ		d'500'/PrSclr1	; time given to 2nd Task during Attn Signal
TSK2MAX 	equ		d'900'/PrSclr1	; time given to 2nd Task after Data Sent/Received
ADBSYNC 	equ		d'72'/PrSclr2	; Sync with extra tolerance after Attn is detected
BIT_TST 	equ		d'50'/PrSclr2	; if time is < 50 = 1 bit, & > 50 = 0 bit
MAX_BIT 	equ		d'72'/PrSclr2	; Maximum time line can be low for a bit   
BITCELL 	equ		d'104'/PrSclr2	; Maximum time for a bit cell = 104 usecs
TLT_MIN 	equ		d'140'/PrSclr2	; Stop to Start minimum time = 140 usecs
TLT_MAX 	equ		d'250'/PrSclr2	; Stop to Start maximum time = 260 usecs
TLT_MID 	equ		d'180'/PrSclr2	; Stop to Start median time  = 208 usecs
SRQ_MAX 	equ		d'296'/PrSclr1	; amount of time to hold for a Service ReQuest 

; NOTE: for RTCC timing of sending bits, some extra time is allowed for 
; instruction cycles between the end of the bit and the start of the next bit

LOW1BIT 	equ		d'22'/PrSclr2	; low time for a 1 bit
HI_1BIT 	equ		d'50'/PrSclr2	; hi time  for a 1 bit
LOW0BIT 	equ		d'56'/PrSclr2	; low time for a 0 bit
HI_0BIT 	equ		d'20'/PrSclr2	; hi time  for a 0 bit

 
; bits of ReqCommand
cmdReset	equ		0
cmdFlush	equ		1
cmdListen	equ		2
cmdTalk		equ		3
cmdReserved	equ		4

reqReg0		equ		0
reqReg1		equ		1
reqReg2		equ		2
reqReg3		equ		3

cblock 20h			; bank0
	
	DeviceAddr
	
	Reg0a
	Reg0b
	Reg1a
	Reg1b
	Reg2a
	Reg2b
	Reg3a
	Reg3b
	
	ShiftReg
	
	TmpReg1			; temporary registers where Data is sent from & 
	TmpReg2			;  received; NOTE: THESE 2 MUST BE IN THIS ORDER
	
	PortTalkBytes:5
	
	RegNum 			; holds current ADB Data Reg.# - NOT a RAM address
	RAMaddr			; holds RAM address of ADB Data Reg.#
	Flags1 			; two Flags registers used by ADB & 2nd
	Flags2 			;   Application Task
	CmdByte			; holds the Command Byte
	BitCounter			; counts down when sending or receiving bits
	Random 			; stores Random Address sent in Talk routine
	TimeVar			; used with RTCC for all ADB timing
	Tsk2Var			; used with RTCC for timing during 2nd Task
	
	ByteCounter
	
	CommandNibble
	CommandCode
	
	
	ReqAddress
	ReqCommand
	ReqReg
	
	
	TmpCtr1			; being used for debounce in example code
	d1				; used in ADC delay loop
	ADCPort			; used in ADC code
	
	
	PortACfg		; 7:6 = 00, 5:4 = AD Config (always 11 for port A), 3:0 = Port Directions (1 = in)
	PortBCfg 		; 7:6 = 00, 5:4 = AD Config (always 11 for port A), 3:0 = Port Directions (1 = in)
	PortAShadow
	PortBShadow
	UnitID			; 7:6 = Unit ID
	
	A1Timer
	A2Timer
	A3Timer
	A4Timer
	
endc


ADBIOPortAShadow	equ	PortBShadow
ADBIOPortBShadow	equ	PortAShadow


cblock 70h			; globals
	SaveStatus
	SaveW
endc