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@@ -0,0 +1,166 @@
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+--- a/Makefile.am
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++++ b/Makefile.am
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+@@ -13,7 +13,7 @@ ethtool_SOURCES += \
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+ fec_8xx.c ibm_emac.c ixgb.c ixgbe.c natsemi.c \
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+ pcnet32.c realtek.c tg3.c marvell.c vioc.c \
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+ smsc911x.c at76c50x-usb.c sfc.c stmmac.c \
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+- sfpid.c sfpdiag.c ixgbevf.c
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++ sfpid.c sfpdiag.c ixgbevf.c ixp4xx.c
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+ endif
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+
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+ TESTS = test-cmdline test-features
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+--- a/ethtool.c
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++++ b/ethtool.c
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+@@ -894,6 +894,7 @@ static const struct {
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+ { "ixgb", ixgb_dump_regs },
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+ { "ixgbe", ixgbe_dump_regs },
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+ { "ixgbevf", ixgbevf_dump_regs },
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++ { "ixp4xx", ixp4xx_dump_regs },
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+ { "natsemi", natsemi_dump_regs },
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+ { "e100", e100_dump_regs },
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+ { "amd8111e", amd8111e_dump_regs },
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+--- a/internal.h
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++++ b/internal.h
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+@@ -243,6 +243,9 @@ int st_gmac_dump_regs(struct ethtool_drv
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+ /* Et131x ethernet controller */
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+ int et131x_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs);
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+
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++/* Intel IXP4xx internal MAC */
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++int ixp4xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs);
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++
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+ /* Rx flow classification */
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+ int rxclass_parse_ruleopts(struct cmd_context *ctx,
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+ struct ethtool_rx_flow_spec *fsp);
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+--- /dev/null
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++++ b/ixp4xx.c
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+@@ -0,0 +1,130 @@
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++/*
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++ * Copyright (c) 2006 Christian Hohnstaed <chohnstaedt@innominate.com>
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++ * This file is released under the GPLv2
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++ */
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++
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++#include <stdio.h>
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++#include "internal.h"
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++
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++#ifndef BIT
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++#define BIT(x) (1<<x)
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++#endif
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++
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++#define TX_CNTRL1_TX_EN BIT(0)
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++#define TX_CNTRL1_DUPLEX BIT(1)
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++#define TX_CNTRL1_RETRY BIT(2)
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++#define TX_CNTRL1_PAD_EN BIT(3)
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++#define TX_CNTRL1_FCS_EN BIT(4)
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++#define TX_CNTRL1_2DEFER BIT(5)
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++#define TX_CNTRL1_RMII BIT(6)
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++
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++/* TX Control Register 2 */
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++#define TX_CNTRL2_RETRIES_MASK 0xf
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++
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++/* RX Control Register 1 */
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++#define RX_CNTRL1_RX_EN BIT(0)
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++#define RX_CNTRL1_PADSTRIP_EN BIT(1)
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++#define RX_CNTRL1_CRC_EN BIT(2)
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++#define RX_CNTRL1_PAUSE_EN BIT(3)
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++#define RX_CNTRL1_LOOP_EN BIT(4)
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++#define RX_CNTRL1_ADDR_FLTR_EN BIT(5)
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++#define RX_CNTRL1_RX_RUNT_EN BIT(6)
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++#define RX_CNTRL1_BCAST_DIS BIT(7)
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++
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++/* Core Control Register */
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++#define CORE_RESET BIT(0)
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++#define CORE_RX_FIFO_FLUSH BIT(1)
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++#define CORE_TX_FIFO_FLUSH BIT(2)
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++#define CORE_SEND_JAM BIT(3)
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++#define CORE_MDC_EN BIT(4)
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++
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++#define MAC "%02x:%02x:%02x:%02x:%02x:%02x"
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++#define MAC_DATA(d) (d)[0], (d)[1], (d)[2], (d)[3], (d)[4], (d)[5]
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++
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++int ixp4xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
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++{
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++ u8 *data = regs->data;
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++
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++ fprintf(stdout,
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++ "TXctrl: 0x%02x:0x%02x\n"
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++ " Enable: %s\n"
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++ " Duplex: %s\n"
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++ " Retry: %s (%d)\n"
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++ " Padding: %s\n"
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++ " Frame check: %s\n"
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++ " TX deferral: %s\n"
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++ " Connection: %s\n"
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++ "\n",
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++ data[0], data[1],
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++ data[0] & TX_CNTRL1_TX_EN ? "yes" : "no",
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++ data[0] & TX_CNTRL1_DUPLEX ? "half" : "full",
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++ data[0] & TX_CNTRL1_RETRY ? "enabled" : "disabled",
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++ data[1] & TX_CNTRL2_RETRIES_MASK,
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++ data[0] & TX_CNTRL1_PAD_EN ? "enabled" : "disabled",
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++ data[0] & TX_CNTRL1_FCS_EN ? "enabled" : "disabled",
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++ data[0] & TX_CNTRL1_2DEFER ? "two-part" : "one-part",
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++ data[0] & TX_CNTRL1_RMII ? "RMII" : "Full MII"
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++ );
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++
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++ fprintf(stdout,
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++ "RXctrl: 0x%02x\n"
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++ " Enable: %s\n"
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++ " Pad strip: %s\n"
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++ " CRC check: %s\n"
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++ " Pause: %s\n"
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++ " Loop: %s\n"
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++ " Promiscous: %s\n"
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++ " Runt frames: %s\n"
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++ " Broadcast: %s\n"
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++ "\n",
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++ data[2],
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++ data[2] & RX_CNTRL1_RX_EN ? "yes" : "no",
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++ data[2] & RX_CNTRL1_PADSTRIP_EN ? "enabled" : "disabled",
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++ data[2] & RX_CNTRL1_CRC_EN ? "enabled" : "disabled",
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++ data[2] & RX_CNTRL1_PAUSE_EN ? "enabled" : "disabled",
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++ data[2] & RX_CNTRL1_LOOP_EN ? "enabled" : "disabled",
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++ data[2] & RX_CNTRL1_ADDR_FLTR_EN ? "disabled" : "enabled",
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++ data[2] & RX_CNTRL1_RX_RUNT_EN ? "forward" : "discard",
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++ data[2] & RX_CNTRL1_BCAST_DIS ? "disabled" : "enabled"
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++ );
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++ fprintf(stdout,
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++ "Core control: 0x%02x\n"
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++ " Core state: %s\n"
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++ " RX fifo: %s\n"
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++ " TX fifo: %s\n"
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++ " Send jam: %s\n"
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++ " MDC clock %s\n"
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++ "\n",
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++ data[32],
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++ data[32] & CORE_RESET ? "reset" : "normal operation",
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++ data[32] & CORE_RX_FIFO_FLUSH ? "flush" : "ok",
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++ data[32] & CORE_TX_FIFO_FLUSH ? "flush" : "ok",
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++ data[32] & CORE_SEND_JAM ? "yes" : "no",
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++ data[32] & CORE_MDC_EN ? "output" : "input"
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++ );
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++ fprintf(stdout,
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++ "MAC addresses: \n"
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++ " Multicast mask: " MAC "\n"
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++ " Multicast address: " MAC "\n"
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++ " Unicast address: " MAC "\n"
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++ "\n",
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++ MAC_DATA(data+13), MAC_DATA(data+19), MAC_DATA(data+26)
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++ );
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++ fprintf(stdout,
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++ "Random seed: 0x%02x\n"
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++ "Threshold empty: %3d\n"
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++ "Threshold full: %3d\n"
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++ "TX buffer size: %3d\n"
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++ "TX deferral: %3d\n"
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++ "RX deferral: %3d\n"
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++ "TX two deferral 1: %3d\n"
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++ "TX two deferral 2: %3d\n"
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++ "Slot time: %3d\n"
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++ "Internal clock: %3d\n"
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++ "\n",
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++ data[4], data[5], data[6], data[7], data[8], data[9],
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++ data[10], data[11], data[12], data[25]
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++ );
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++
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++ return 0;
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++}
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