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+/*
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+ * Author: Jon Trulson <jtrulson@ics.com>
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+ * Copyright (c) 2015 Intel Corporation.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining
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+ * a copy of this software and associated documentation files (the
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+ * "Software"), to deal in the Software without restriction, including
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+ * without limitation the rights to use, copy, modify, merge, publish,
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+ * distribute, sublicense, and/or sell copies of the Software, and to
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+ * permit persons to whom the Software is furnished to do so, subject to
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+ * the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+#pragma once
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+
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+#include <string>
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+#include <mraa/i2c.hpp>
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+
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+#define H3LIS331DL_I2C_BUS 0
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+#define H3LIS331DL_DEFAULT_I2C_ADDR 0x18
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+
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+namespace upm {
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+
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+ /**
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+ * @brief Grove 3-axis I2C Accelerometer (400G)
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+ * @defgroup h3lis331dl libupm-h3lis331dl
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+ * @ingroup seeed i2c accelerometer
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+ */
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+
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+ /**
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+ * @library h3lis331dl
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+ * @sensor h3lis331dl
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+ * @comname Grove 3-axis I2C Accelerometer (400G)
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+ * @type accelerometer
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+ * @man seeed
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+ * @web http://www.seeedstudio.com/depot/Grove-3Axis-Digital-Accelerometer400g-p-1897.html
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+ * @con i2c
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+ *
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+ * @brief C++ API for the H3LIS331DL based Grove 3-axis I2C Accelerometer
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+ * (400G)
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+ *
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+ * @image html h3lis331dl.jpg
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+ * @snippet h3lis331dl.cxx Interesting
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+ */
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+ class H3LIS331DL {
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+ public:
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+
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+ /**
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+ * H3LIS331DL registers
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+ */
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+ typedef enum {
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+ // Reserved bytes must not be written into as they contain
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+ // factory calibration data. Changing those values may lead to
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+ // improper functioning of the device.
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+
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+ // 0x00-0x0E reserved
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+
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+ REG_WHOAMI = 0x0f,
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+
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+ // 0x10-0x1f reserved
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+
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+ REG_REG1 = 0x20,
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+ REG_REG2 = 0x21,
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+ REG_REG3 = 0x22,
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+ REG_REG4 = 0x23,
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+ REG_REG5 = 0x24,
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+
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+ REG_HP_FILTER_RESET = 0x25,
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+ REG_REFERENCE = 0x26,
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+
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+ REG_STATUS = 0x27,
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+
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+ REG_OUT_X_L = 0x28,
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+ REG_OUT_X_H = 0x29,
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+ REG_OUT_Y_L = 0x2a,
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+ REG_OUT_Y_H = 0x2b,
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+ REG_OUT_Z_L = 0x2c,
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+ REG_OUT_Z_H = 0x2d,
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+
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+ // 0x2e, 0x2f reserved
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+
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+ REG_INT1_CFG = 0x30,
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+ REG_INT1_SRC = 0x31,
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+ REG_INT1_THS = 0x32,
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+ REG_INT1_DUR = 0x33,
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+
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+ REG_INT2_CFG = 0x34,
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+ REG_INT2_SRC = 0x35,
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+ REG_INT2_THS = 0x36,
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+ REG_INT2_DUR = 0x37,
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+
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+ // 0x38-0x3f reserved
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+ } H3LIS331DL_REG_T;
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+
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+ /**
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+ * REG1 bits
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+ */
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+ typedef enum {
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+ REG1_XEN = 0x01, // X axis enable
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+ REG1_YEN = 0x02,
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+ REG1_ZEN = 0x04,
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+
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+ REG1_DR0 = 0x08, // data rate
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+ REG1_DR1 = 0x10,
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+ REG1_DR_SHIFT = 3, // DR shift
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+
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+ REG1_PM0 = 0x20, // power mode
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+ REG1_PM1 = 0x40,
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+ REG1_PM2 = 0x80,
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+ REG1_PM_SHIFT = 5
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+ } REG1_BITS_T;
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+
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+ /**
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+ * REG1 DR (output rate) bits
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+ */
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+ typedef enum {
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+ DR_50_37 = 0x0, // 50Hz output with 37Hz LPF cutoff
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+ DR_100_74 = 0x1,
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+ DR_400_292 = 0x2,
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+ DR_1000_780 = 0x3
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+ } DR_BITS_T;
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+
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+ /**
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+ * REG1 PM (Power mode) bits
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+ */
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+ typedef enum {
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+ PM_POWERDWN = 0x0,
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+ PM_NORMAL = 0x1,
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+ PM_LP05 = 0x2, // .5 updates/sec
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+ PM_LP1 = 0x3, // 1 update/sec
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+ PM_LP2 = 0x4,
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+ PM_LP5 = 0x5,
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+ PM_LP10 = 0x6
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+ } PM_BITS_T;
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+
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+ /**
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+ * REG2 bits
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+ */
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+ typedef enum {
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+ REG2_HPCF0 = 0x01,
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+ REG2_HPCF1 = 0x02,
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+ REG2_HPCF_SHIFT = 0,
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+
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+ REG2_HPEN1 = 0x04,
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+ REG2_HPEN2 = 0x08,
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+ REG2_FDS = 0x10,
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+
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+ REG2_HPM0 = 0x20,
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+ REG2_HPM1 = 0x40,
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+ REG2_HPM_SHIFT = 5,
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+
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+ REG2_BOOT = 0x80
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+ } REG2_BITS_T;
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+
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+ /**
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+ * REG2 HPCF (High Pass Cutoff Frequency) bits
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+ */
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+ typedef enum {
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+ HPCF_8 = 0x0,
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+ HPCF_16 = 0x1,
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+ HPCF_32 = 0x2,
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+ HPCF_64 = 0x3,
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+ } HPCF_BITS_T;
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+
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+ /**
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+ * REG2 HPM (High Pass Filter Mode) bits
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+ */
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+ typedef enum {
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+ HPM_NORMAL0 = 0x0,
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+ HPM_REF = 0x1,
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+ HPM_NORMAL1 = 0x2
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+ } HPM_BITS_T;
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+
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+ /**
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+ * REG3 bits
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+ */
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+ typedef enum {
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+ REG3_I1_CFG0 = 0x01,
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+ REG3_I1_CFG1 = 0x02,
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+ REG3_I1_CFG_SHIFT = 0,
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+
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+ REG3_LIR1 = 0x04,
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+
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+ REG3_I2_CFG0 = 0x08,
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+ REG3_I2_CFG1 = 0x10,
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+ REG3_I2_CFG_SHIFT = 3,
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+
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+ REG3_LIR2 = 0x20,
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+ REG3_PP_OD = 0x40,
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+ REG3_IHL = 0x80
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+ } REG3_BITS_T;
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+
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+ /**
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+ * REG3 I1/I2 PAD control bits
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+ */
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+ typedef enum {
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+ I_SRC = 0x0, // INT source
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+ I_OR = 0x1, // INT1 OR INT2 source
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+ I_DR = 0x2, // Data Ready
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+ I_BOOTING = 0x3 // Boot is running
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+ } I_CFG_BITS_T;
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+
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+ /**
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+ * REG4 bits
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+ */
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+ typedef enum {
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+ REG4_SIM = 0x01, // SPI 4 or 3 wire
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+
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+ // bits 01,02,04 reserved
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+
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+ REG4_FS0 = 0x10,
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+ REG4_FS1 = 0x20,
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+ REG4_FS_SHIFT = 4,
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+
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+ REG4_BLE = 0x40, // big/little endian
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+ REG4_BDU = 0x80 // Block data update
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+ } REG4_BITS_T;
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+
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+ /**
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+ * REG4 FS (Full Scale) bits
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+ */
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+ typedef enum {
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+ FS_100 = 0x0, // 100g scale
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+ FS_200 = 0x1, // 200g scale
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+ FS_400 = 0x3 // 400g scale
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+ } FS_BITS_T;
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+
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+ /**
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+ * REG5 TURNON (sleep to wake) bits
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+ */
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+ typedef enum {
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+ REG5_TURNON0 = 0x01, // turnon mode for sleep-to-wake
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+ REG5_TURNON1 = 0x02
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+
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+ // bits 04-80 reserved
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+ } REG5_BITS_T;
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+
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+ /**
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+ * STATUS bits
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+ */
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+ typedef enum {
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+ STATUS_XDA = 0x01, // X data available
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+ STATUS_YDA = 0x02,
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+ STATUS_ZDA = 0x04,
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+ STATUS_ZYXDA = 0x08, // X, Y, and Z data available
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+ STATUS_XOR = 0x10, // X overrun
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+ STATUS_YOR = 0x20,
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+ STATUS_ZOR = 0x40,
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+ STATUS_ZYXOR = 0x80 // X, Y, and Z data overrun
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+ } STATUS_BITS_T;
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+
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+ /**
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+ * INT1/INT2 CFG bits
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+ */
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+ typedef enum {
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+ INT_CFG_XLIE = 0x01, // enable intr on low X event
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+ INT_CFG_XHIE = 0x02, // enable intr on high X event
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+ INT_CFG_YLIE = 0x04,
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+ INT_CFG_YHIE = 0x08,
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+ INT_CFG_ZLIE = 0x10,
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+ INT_CFG_ZHIE = 0x20,
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+ // 0x40 reserved
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+ INT_CFG_AOI = 0x80 // AND or OR combination or intrs
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+ } INT_CFG_BITS_T;
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+
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+ /**
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+ * INT1/INT2 SRC bits
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+ */
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+ typedef enum {
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+ INT_SRC_XL = 0x01, // X low intr event
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+ INT_SRC_XH = 0x02, // X high intr event
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+ INT_SRC_YL = 0x04,
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+ INT_SRC_YH = 0x08,
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+ INT_SRC_ZL = 0x10,
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+ INT_SRC_ZH = 0x20,
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+ INT_SRC_IA = 0x40 // Interrupt generated (active)
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+ // 0x80 reserved
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+ } INT_SRC_BITS_T;
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+
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+ /**
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+ * h3lis331dl constructor
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+ *
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+ * @param bus i2c bus to use
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+ * @param address the address for this device
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+ */
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+ H3LIS331DL(int bus, uint8_t address = H3LIS331DL_DEFAULT_I2C_ADDR);
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+
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+ /**
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+ * H3LIS331DL Destructor
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+ */
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+ ~H3LIS331DL();
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+
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+ /**
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+ * set up initial values and start operation
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+ *
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+ * @param odr the data rate: one of the DR_BITS_T values
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+ * @param pm the power mode: one of the PM_BITS_T values
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+ * @param fs the FullScale: one of the FS_BITS_T values
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+ * @return true if successful
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+ */
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+ bool init(DR_BITS_T odr=DR_50_37, PM_BITS_T pm=PM_NORMAL,
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+ FS_BITS_T fs=FS_100);
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+
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+ /**
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+ * read and return the Chip ID (WHO_AM_I register)
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+ *
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+ * @return true if successful
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+ */
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+ uint8_t getChipID();
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+
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+ /**
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+ * set the output data rate
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+ *
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+ * @param one of the DR_BITS_T values
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+ * @return true if successful
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+ */
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+ bool setDataRate(DR_BITS_T odr);
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+
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+ /**
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+ * set the power mode
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+ *
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+ * @param one of the PM_BITS_T values
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+ * @return true if successful
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+ */
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+ bool setPowerMode(PM_BITS_T pm);
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+
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+ /**
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+ * enable one or more of the 3 axes. The arguement is a bitmsk
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+ * composed of REG1_XEN, REG1_YEN and/or REG1_ZEN corresponding
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+ * the axes you want enabled.
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+ *
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+ * @param axisEnable bitmask of axes to enable
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+ * (REG1_XEN | REG1_YEN | REG1_ZEN)
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+ * @return true if successful
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+ */
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+ bool enableAxis(uint8_t axisEnable);
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+
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+ /**
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+ * set the scaling factor to 100, 200, or 400G's
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+ *
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+ * @param fs one of the FS_BITS_T values
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+ * @return true if successful
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+ */
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+ bool setFullScale(FS_BITS_T fs);
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+
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+ /**
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+ * set high pass cutoff filter
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+ *
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+ * @param val one of the HPCF_BITS_T values
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+ * @return true if successful
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+ */
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+ bool setHPCF(HPCF_BITS_T val);
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+
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+ /**
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+ * set high pass filter mode
|
|
366
|
+ *
|
|
367
|
+ * @param val one of the HPM_BITS_T values
|
|
368
|
+ * @return true if successful
|
|
369
|
+ */
|
|
370
|
+ bool setHPM(HPM_BITS_T val);
|
|
371
|
+
|
|
372
|
+ /**
|
|
373
|
+ * boot the device. Booting the device causes internal flash
|
|
374
|
+ * calibration values to be reloaded into the visible registers,
|
|
375
|
+ * in the event they have been corrupted. This function will
|
|
376
|
+ * return when boot is complete.
|
|
377
|
+ *
|
|
378
|
+ * @return true if successful
|
|
379
|
+ */
|
|
380
|
+ bool boot();
|
|
381
|
+
|
|
382
|
+ /**
|
|
383
|
+ * enable high pass filter for interrupt 1 source
|
|
384
|
+ *
|
|
385
|
+ * @param enable true to enable the filter, false otherwise
|
|
386
|
+ * @return true if successful
|
|
387
|
+ */
|
|
388
|
+ bool enableHPF1(bool enable);
|
|
389
|
+
|
|
390
|
+ /**
|
|
391
|
+ * enable high pass filter for interrupt 2 source
|
|
392
|
+ *
|
|
393
|
+ * @param enable true to enable the filter, false otherwise
|
|
394
|
+ * @return true if successful
|
|
395
|
+ */
|
|
396
|
+ bool enableHPF2(bool enable);
|
|
397
|
+
|
|
398
|
+ /**
|
|
399
|
+ * enable filtered data selection
|
|
400
|
+ *
|
|
401
|
+ * @param enable true to enable, false otherwise
|
|
402
|
+ * @return true if successful
|
|
403
|
+ */
|
|
404
|
+ bool enableFDS(bool enable);
|
|
405
|
+
|
|
406
|
+ /**
|
|
407
|
+ * set interrupts to be active low instead of high
|
|
408
|
+ *
|
|
409
|
+ * @param enable true to enable, false otherwise
|
|
410
|
+ * @return true if successful
|
|
411
|
+ */
|
|
412
|
+ bool setInterruptActiveLow(bool enable);
|
|
413
|
+
|
|
414
|
+ /**
|
|
415
|
+ * set interrupt output mode to open drain rather than push/pull
|
|
416
|
+ *
|
|
417
|
+ * @param enable true to enable, false otherwise
|
|
418
|
+ * @return true if successful
|
|
419
|
+ */
|
|
420
|
+ bool setInterruptOpenDrain(bool enable);
|
|
421
|
+
|
|
422
|
+ /**
|
|
423
|
+ * set interrupt 1 latch enable
|
|
424
|
+ *
|
|
425
|
+ * @param enable true to enable, false otherwise
|
|
426
|
+ * @return true if successful
|
|
427
|
+ */
|
|
428
|
+ bool setInterrupt1Latch(bool enable);
|
|
429
|
+
|
|
430
|
+ /**
|
|
431
|
+ * set interrupt 2 latch enable
|
|
432
|
+ *
|
|
433
|
+ * @param enable true to enable, false otherwise
|
|
434
|
+ * @return true if successful
|
|
435
|
+ */
|
|
436
|
+ bool setInterrupt2Latch(bool enable);
|
|
437
|
+
|
|
438
|
+ /**
|
|
439
|
+ * set the interrupt 1 pad configuration
|
|
440
|
+ *
|
|
441
|
+ * @param val one fo the I_CFG_BITS_T values
|
|
442
|
+ * @return true if successful
|
|
443
|
+ */
|
|
444
|
+ bool setInterrupt1PadConfig(I_CFG_BITS_T val);
|
|
445
|
+
|
|
446
|
+ /**
|
|
447
|
+ * set the interrupt 2 pad configuration
|
|
448
|
+ *
|
|
449
|
+ * @param val one fo the I_CFG_BITS_T values
|
|
450
|
+ * @return true if successful
|
|
451
|
+ */
|
|
452
|
+ bool setInterrupt2PadConfig(I_CFG_BITS_T val);
|
|
453
|
+
|
|
454
|
+ /**
|
|
455
|
+ * enable block data update. When enabled, low/high output
|
|
456
|
+ * registers are not update until both low and high values have
|
|
457
|
+ * been read.
|
|
458
|
+ *
|
|
459
|
+ * @param enable true to enable, false otherwise
|
|
460
|
+ * @return true if successful
|
|
461
|
+ */
|
|
462
|
+ bool enableBDU(bool enable);
|
|
463
|
+
|
|
464
|
+ /**
|
|
465
|
+ * enable big endian output for 16b reads
|
|
466
|
+ *
|
|
467
|
+ * @param enable true to enable, false otherwise
|
|
468
|
+ * @return true if successful
|
|
469
|
+ */
|
|
470
|
+ bool enableBLE(bool enable);
|
|
471
|
+
|
|
472
|
+ /**
|
|
473
|
+ * enable sleep to wake functionality.
|
|
474
|
+ *
|
|
475
|
+ * @param enable true to enable, false otherwise
|
|
476
|
+ * @return true if successful
|
|
477
|
+ */
|
|
478
|
+ bool enableSleepToWake(bool enable);
|
|
479
|
+
|
|
480
|
+ /**
|
|
481
|
+ * return the contents of the REG_STATUS register
|
|
482
|
+ *
|
|
483
|
+ * @return the contents of the REG_STATUS register
|
|
484
|
+ */
|
|
485
|
+ uint8_t getStatus();
|
|
486
|
+
|
|
487
|
+ /**
|
|
488
|
+ * setup the interrupt 1 config register
|
|
489
|
+ *
|
|
490
|
+ * @param val a bitmask of desired INT_CFG_BITS_T bits
|
|
491
|
+ * @return true if successful
|
|
492
|
+ */
|
|
493
|
+ bool setInterrupt1Config(uint8_t val);
|
|
494
|
+
|
|
495
|
+ /**
|
|
496
|
+ * setup the interrupt 2 config register
|
|
497
|
+ *
|
|
498
|
+ * @param val a bitmask of desired INT_CFG_BITS_T bits
|
|
499
|
+ * @return true if successful
|
|
500
|
+ */
|
|
501
|
+ bool setInterrupt2Config(uint8_t val);
|
|
502
|
+
|
|
503
|
+ /**
|
|
504
|
+ * setup the interrupt 1 source register
|
|
505
|
+ *
|
|
506
|
+ * @param val a bitmask of desired INT_SRC_BITS_T bits
|
|
507
|
+ * @return true if successful
|
|
508
|
+ */
|
|
509
|
+ bool setInterrupt1Source(uint8_t val);
|
|
510
|
+
|
|
511
|
+ /**
|
|
512
|
+ * setup the interrupt 2 source register
|
|
513
|
+ *
|
|
514
|
+ * @param val a bitmask of desired INT_SRC_BITS_T bits
|
|
515
|
+ * @return true if successful
|
|
516
|
+ */
|
|
517
|
+ bool setInterrupt2Source(uint8_t val);
|
|
518
|
+
|
|
519
|
+ /**
|
|
520
|
+ * setup the interrupt 1 threshold register
|
|
521
|
+ *
|
|
522
|
+ * @param val the threshhold to set
|
|
523
|
+ * @return true if successful
|
|
524
|
+ */
|
|
525
|
+ bool setInterrupt1Threshold(uint8_t val);
|
|
526
|
+
|
|
527
|
+ /**
|
|
528
|
+ * setup the interrupt 2 threshold register
|
|
529
|
+ *
|
|
530
|
+ * @param val the threshhold to set
|
|
531
|
+ * @return true if successful
|
|
532
|
+ */
|
|
533
|
+ bool setInterrupt2Threshold(uint8_t val);
|
|
534
|
+
|
|
535
|
+ /**
|
|
536
|
+ * setup the interrupt 1 duration register
|
|
537
|
+ *
|
|
538
|
+ * @param val the duration to set
|
|
539
|
+ * @return true if successful
|
|
540
|
+ */
|
|
541
|
+ bool setInterrupt1Duration(uint8_t val);
|
|
542
|
+
|
|
543
|
+ /**
|
|
544
|
+ * setup the interrupt 2 duration register
|
|
545
|
+ *
|
|
546
|
+ * @param val the duration to set
|
|
547
|
+ * @return true if successful
|
|
548
|
+ */
|
|
549
|
+ bool setInterrupt2Duration(uint8_t val);
|
|
550
|
+
|
|
551
|
+ /**
|
|
552
|
+ * read the sensor and store current values internally
|
|
553
|
+ */
|
|
554
|
+ void update();
|
|
555
|
+
|
|
556
|
+ /**
|
|
557
|
+ * set adjustment offsets for each of the axes. This can be used
|
|
558
|
+ * for calibration. The values supplied here will be subtracted
|
|
559
|
+ * from the axis data read from the device.
|
|
560
|
+ *
|
|
561
|
+ * @param adjX the amount by which to correct the X axis measurement
|
|
562
|
+ * @param adjY the amount by which to correct the Y axis measurement
|
|
563
|
+ * @param adjZ the amount by which to correct the Z axis measurement
|
|
564
|
+ */
|
|
565
|
+ void setAdjustmentOffsets(int adjX, int adjY, int adjZ);
|
|
566
|
+
|
|
567
|
+ /**
|
|
568
|
+ * get the acceleration values for each of the axes
|
|
569
|
+ *
|
|
570
|
+ * @param aX the returned X acceleration
|
|
571
|
+ * @param aY the returned Y acceleration
|
|
572
|
+ * @param aZ the returned Z acceleration
|
|
573
|
+ */
|
|
574
|
+ void getAcceleration(float *aX, float *aY, float *aZ);
|
|
575
|
+
|
|
576
|
+ /**
|
|
577
|
+ * get the raw axis values
|
|
578
|
+ *
|
|
579
|
+ * @param x the returned raw X value
|
|
580
|
+ * @param y the returned raw Y value
|
|
581
|
+ * @param z the returned raw Z value
|
|
582
|
+ */
|
|
583
|
+ void getRawXYZ(int *x, int *y, int *z);
|
|
584
|
+
|
|
585
|
+ /**
|
|
586
|
+ * get the adjusted axis values
|
|
587
|
+ *
|
|
588
|
+ * @param x the returned X value
|
|
589
|
+ * @param y the returned Y value
|
|
590
|
+ * @param z the returned Z value
|
|
591
|
+ */
|
|
592
|
+ void getXYZ(int *x, int *y, int *z);
|
|
593
|
+
|
|
594
|
+ /**
|
|
595
|
+ * provide public access to the class's MRAA i2C context for
|
|
596
|
+ * direct user access
|
|
597
|
+ *
|
|
598
|
+ * @return a reference to the class i2c context
|
|
599
|
+ */
|
|
600
|
+ mraa::I2c& i2cContext() { return m_i2c; };
|
|
601
|
+
|
|
602
|
+
|
|
603
|
+ protected:
|
|
604
|
+ int16_t m_rawX, m_rawY, m_rawZ;
|
|
605
|
+ int16_t m_adjX, m_adjY, m_adjZ;
|
|
606
|
+ mraa::I2c m_i2c;
|
|
607
|
+
|
|
608
|
+ private:
|
|
609
|
+ uint8_t m_addr;
|
|
610
|
+ };
|
|
611
|
+}
|
|
612
|
+
|
|
613
|
+
|